Hoang Le

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Papers by Hoang Le

The Next Generation of Regenerative Catalytic Breakers for Use in Alkaline and High-Temperature Fracturing Fluids

by Qi Qu and Hoang Le

SPE International Symposium and Exhibiton on Formation Damage Control, 2010

Compositions and methods for modifying the permeability of subterranean formations

Method for treating subterranean formation with enhanced viscosity foam

$Research paper thumbnail of Breaker system for fracturing fluids used in fracturing oil bearing formations$

Breaker system for fracturing fluids used in fracturing oil bearing formations

Ninjurin1 regulates lipopolysaccharide-induced inflammation through direct binding

International journal of oncology, Jan 15, 2015

Ninjurin1 is a transmembrane protein involved in macrophage migration and adhesion during inflamm... more Ninjurin1 is a transmembrane protein involved in macrophage migration and adhesion during inflammation. It was recently reported that repression of Ninjurin1 attenuated the lipopolysaccharide (LPS)-induced inflammatory response in macrophages; however, the precise mechanism by which Ninjurin1 modulates LPS-induced inflammation remains poorly understood. In the present study, we found that the interaction between Ninjurin1 and LPS contributed to the LPS-induced inflammatory response. Notably, pull-down assays using lysates from HEK293T cells transfected with human or mouse Ninjurin1 and biotinylated LPS (LPS-biotin) showed that LPS directly bound Ninjurin1. Subsequently, LPS binding assays with various truncated forms of Ninjurin1 protein revealed that amino acids (aa) 81-100 of Ninjurin1 were required for LPS binding. In addition, knockdown experiments using Ninj1 siRNA resulted in decreased nitric oxide (NO) and tumor necrosis factor-α (TNFα) secretion upon LPS treatment in Raw264....

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, 2009

Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. ... more Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-of-theart designs cannot support the current largest routing table (consisting of 257K prefixes in backbone routers). We propose a novel scalable high-throughput, low-power SRAMbased linear pipeline architecture for IP lookup. Using a single FPGA, the proposed architecture can support the current largest routing table, or even larger tables of up to 400K prefixes. Our architecture can also be easily partitioned, so as to use external SRAM to handle even larger routing tables (up to . Our implementation shows a high throughput (340 mega lookups per second or 109 Gbps), even when external SRAM is used. The use of SRAM (instead of TCAM) leads to an order of magnitude reduction in power dissipation. Additionally, the architecture supports power saving by allowing only a portion of the memory to be active on each memory access. Our design also maintains packet input order and supports in-place non-blocking route updates.

format_quoteAddressed key challenges in IP packet forwarding with high-throughput SMB-based architecture optimizing power consumption and scalability.format_quote

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High-throughput IP-lookup supporting dynamic routing tables using FPGA

Advances in optical networking technology are pushing internet link rates up to 100 Gbps. Such li... more Advances in optical networking technology are pushing internet link rates up to 100 Gbps. Such line rates demand a throughput of over 150 million packets per second at core routers. Along with the increase in link speed, the size of the dynamic routing table of these core routers is also increasing at the rate of 25-50 K additional prefixes per year. These dynamic tables require high prefix deletion and insertion rates. Therefore, rapid prefix update without disrupting router operation has also emerged as a critical requirement. Furthermore, IPv6 standard extends the current IPv4 prefix length from 32 to 128 bits. Thus, it is a major challenge to scale the existing solutions to simultaneously support increased throughput, table size, prefix length and rapid update. While the existing solutions can achieve high throughput, they cannot support large routing tables and rapid update at the same time. We propose a novel scalable, high-throughput linear pipeline architecture for IP-lookup...

Bidirectional Pipelining for Scalable IP Lookup and Packet Classification

Both IP lookup and packet classification in IP routers can be implemented by some form of tree tr... more Both IP lookup and packet classification in IP routers can be implemented by some form of tree traversal. SRAM-based Pipelining can improve the throughput dramatically. However, previous pipelining schemes result in unbalanced memory allocation over the pipeline stages. This has been identified as a major challenge for scalable pipelined solutions. This paper proposes a flexible bidirectional linear pipeline architecture based on widely-used dual-port SRAMs. A search tree is partitioned, and then mapped onto pipeline stages by a bidirectional fine-grained mapping scheme. We introduce the notion of inversion factor and several heuristics to invert subtrees for memory balancing. Due to its linear structure, the architecture maintains packet input order, and supports non-blocking route updates. Our experiments show that, the architecture can achieve a perfectly balanced memory distribution over the pipeline stages, for both trie-based IP lookup and tree-based multi-dimensional packet c...

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Energy efficient parameterized FFT architecture

In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs o... more In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. A parameterized FFT architecture is proposed to identify the design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize decomposition based FFT algorithms. Then we explore an energy efficient design by empirical selection on the values of the chosen architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The trade offs between energy, area, and time are analyzed using two performance metrics: the energy efficiency (defined as the number of operations per Joule) and the Energy×Area×Time (EAT) composite metric. From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. F...

Development and Field Application of a Low-pH, Efficient Fracturing Fluid for Western Siberian Oil and Gas Wells

SPE Russian Oil and Gas Technical Conference and Exhibition, 2008

Optimizing Decomposition-Based Packet Classification Implementation on FPGAs

2011 International Conference on Reconfigurable Computing and FPGAs, 2011

ABSTRACT Hardware implementations of Internet Protocol (IP) classification algorithms have been p... more ABSTRACT Hardware implementations of Internet Protocol (IP) classification algorithms have been proposed by the research community over the years to realize high speed routers and Internet backbone. Decomposition-based IP classification algorithms are desirable for hardware implementation due to their parallel search on multiple fields. These algorithms consist of two phases: independent searches on each packet field in the first phase followed by the second phase where the results from the first phase are combined. However, the primary challenge in implementing this high-level approach lies in the second phase, i.e. how to efficiently combine the results of the single field searches. In this paper, we propose a systolic-array-based architecture on FPGA focusing on the combining techniques in phase two. The proposed approach exploits the rich logic resources on FPGA and achieves high throughput by deeply pipelining the architecture. We show the area analysis of the design to demonstrate the efficiency in on-chip resource usage. We also experimentally evaluate the impact of the size of the input rule set and number of matching rules from first phase on the performance of our design. We compare our design against the Bit Vector algorithm, another decomposition-based classification method, and demonstrate that our design is more efficient with respect to logic resource usage and is feasible for large rule sets. Post place and route result using a state-of-the-art FPGA device shows that the design can sustain a throughput of 107 Gbps, for a rule set consisting of up to 64K rules.

A Memory-Efficient and Modular Approach for String Matching on FPGAs

In Network Intrusion Detection Systems (NIDSs), string matching demands exceptionally high perfor... more In Network Intrusion Detection Systems (NIDSs), string matching demands exceptionally high performance to match the content of network traffic against a predefined database of malicious patterns. Much work has been done in this field; however, they result in low memory efficiency 1 . Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-ofthe-art designs cannot support large dictionaries without using high-latency external DRAM. We propose a novel Memory efficient Architecture for large-scale String Matching (MASM), based on pipelined binary search tree. With memory efficiency close to 1 byte/char, MASM can support a dictionary 2 of over 4 MBytes, using a single FPGA device. The architecture can also be easily partitioned, so as to use external SRAM to handle even larger dictionaries of over 8 MBytes. Our implementation results show a sustained throughput of 3.5 Gbps, even when external SRAM is used. The MASM module can be simply duplicated to accept multiple characters per cycle, leading to scalable throughput with respect to the number of characters processed in each cycle. Dictionary update involves only rewriting the memory content, which can be done quickly without reconfiguring the chip.

format_quoteMASM's architecture utilizes a binary search tree to improve storage efficiency, enabling offloading to external SRAM.format_quote

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Memory efficient string matching

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10, 2010

ABSTRACT Network Intrusion Detection Systems (NIDSs) have emerged as powerful tools for detecting... more ABSTRACT Network Intrusion Detection Systems (NIDSs) have emerged as powerful tools for detecting and preventing malicious attacks over both the Internet and Intranet. String matching, which is one of the most important functions of NIDS, demands exceptionally high performance to match the content of network traffic against a predefined database of malicious patterns. Much work has been done in this field; however, they result in low memory efficiency\footnote{The memory efficiency (in bytes/char) is defined as the ratio of the amount of the required storage memory (in bytes), and the size of the dictionary (number of characters).}. Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-of-the-art designs cannot support large dictionaries without using high-latency external DRAM. We propose a novel Memory efficient Architecture for large-scale String Matching, namely MASM, based on pipelined binary search tree. Our design provides a high-throughput matching module, which can be used as the building block to process arbitrary-length patterns. With memory efficiency close to 1 byte/char, MASM can support a dictionary\footnote The size of a dictionary is the total number of characters in all the patterns in the dictionary. of over 4 MB (regardless of the size of the alphabet), using a single state-of-the-art FPGA device. This efficiency is comparable to that of a Ternary Content Addressable Memory (TCAM)-based solution. The architecture can also be easily partitioned, so as to use external SRAM to handle even larger dictionaries of over 8 MB. Our implementation results show a sustained throughput of 3.2 Gbps, even when external SRAM is used. The MASM module can be simply duplicated to accept multiple characters per cycle, leading to scalable throughput with respect to the number of characters processed in each cycle. Dictionary update involves only rewriting the memory content, which can be done quickly without reconfiguring the chip.

Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA

2011 21st International Conference on Field Programmable Logic and Applications, 2011

ABSTRACT Most current SRAM-based high-speed Internet Protocol (IP) packet classification implemen... more ABSTRACT Most current SRAM-based high-speed Internet Protocol (IP) packet classification implementations use tree traversal and pipelining. However, these approaches result in inefficient memory utilization. Due to the limited amount of on-chip memory of the state-of-the-art Field Programmable Gate Arrays (FPGAs), existing designs cannot support large filter databases arising in backbone routers and intrusion detection systems. Hierarchical search structures for packet classification exhibit good memory performance and support quick rule update. However, pipelined hardware implementation of these algorithms suffer from inefficient resource and memory usage due to variation in the size of the trie nodes and backtracking. We propose a memory efficient organization denoted Clustered Hierarchical Search Structure (CHSS) for packet classification. We present a clustering algorithm that partitions a given filter database to reduce the memory requirement. We show that, using the resulting structure, backtracking is not needed to perform a search. We introduce two parameters (NRtrie, NRtree), which can be chosen based on the given filter database to achieve good memory efficiency. Our algorithm demonstrates substantial reduction in the memory footprint compared with the state-of-the-art. For all publicly available filter databases, the achieved memory efficiency is between 21.54 and 41.25 bytes per rule. We map the proposed data structure onto a linear pipeline architecture to achieve high throughput. Post place and route result using a state-of-the-art FPGA device shows that the design can sustain a throughput of 408 million packets per second, or 130.5 Gbps (for the minimum packet size of 40 Bytes).

Hybrid data structure for IP lookup in virtual routers using FPGAs

ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, 2011

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Hierarchical hybrid search structure for high performance packet classification

2012 Proceedings IEEE INFOCOM, 2012

ABSTRACT Hierarchical search structures for packet classification offer good memory performance a... more ABSTRACT Hierarchical search structures for packet classification offer good memory performance and support quick rule updates when implemented on multi-core network processors. However, pipelined hardware implementation of these algorithms has two disadvantages: (1) backtracking which requires stalling the pipeline and (2) inefficient memory usage due to variation in the size of the trie nodes. We propose a clustering algorithm that can partition a given rule database into a fixed number of clusters to eliminate back-tracking in the state-of-the-art hierarchical search structures. Furthermore, we develop a novel ternary trie data structure (T∈). In T∈ structure, the size of the trie nodes is fixed by utilizing ∈-branch property, which overcomes the memory inefficiency problems in the pipelined hardware implementation of hierarchical search structures. We design a two-stage hierarchical search structure consisting of binary search trees in Stage 1, and T∈ structures in Stage 2. Our approach demonstrates a substantial reduction in the memory footprint compared with that of the state-of-the-art. For all publicly available databases, the achieved memory efficiency is between 10.37 and 22.81 bytes of memory per rule. State-of-the-art designs can only achieve the memory efficiency of over 23 byte/rule in the best case. We also propose a SRAM-based linear pipelined architecture for packet classification that achieves high throughput. Using a state-of-the-art FPGA, the proposed design can sustain a 418 million packets per second throughput or 134 Gbps (for the minimum packet size of 40 Bytes). Additionally, our design maintains packet input order and supports in-place non-blocking rule updates.

Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. ... more Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available on-chip memory and pin limitations of FPGAs, stateof-the-art designs on FPGAs cannot support large routing tables arising in backbone routers. Therefore, ternary content addressable memory (TCAM) is widely used. We propose a novel SRAM-based linear pipeline architecture, named DuPI. Using a single Virtex-4, DuPI can support a routing table of up to 228K prefixes, which is 3× the state-of-the-art. Our architecture can also be easily partitioned, so as to use external SRAM to handle even larger routing tables (up to 2 M prefixes), while maintaining a 324 MLPS throughput. The use of SRAM (instead of TCAM) leads to orders of magnitude of reduction in power dissipation. Employing caching to exploit Internet traffic locality, we can achieve a throughput of 1.3 GLPS (billion lookups per second). Our design also maintains packet input order, and supports in-place nonblocking route updates.

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A SRAM-based architecture for trie-based IP lookup using FPGA

Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08, 2008

Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipel... more Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbalanced memory allocation over the pipeline stages. This has been identified as a major challenge for pipelined solutions. In this paper, an IP lookup rate of 325 MLPS (millions lookups per second) is achieved using a novel SRAM-based bidirectional optimized linear pipeline architecture on Field Programmable Gate Array, named BiOLP, for tree-based search engines in IP routers. BiOLP can also achieve a perfectly balanced memory distribution over the pipeline stages. Moreover, by employing caching to exploit the Internet traffic locality, BiOLP can achieve a high throughput of up to 1.3 GLPS (billion lookups per second). It also maintains packet input order, and supports route updates without blocking subsequent incoming packets.

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Memory-efficient IPv4/v6 lookup on FPGAs using distance-bounded path compression

Proceedings - IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, 2011

Abstract Memory efficiency with compact data structures for Internet Protocol (IP) lookup has rec... more Abstract Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially arising in the next generation IPv6 routing protocol. Due to longer prefix and much larger address space, straight-forward implementation of ...

Evaluating energy efficiency of floating point matrix multiplication on FPGAs

2013 IEEE High Performance Extreme Computing Conference (HPEC), 2013

ABSTRACT Energy efficiency has emerged as one of the key performance metrics in scientific comput... more ABSTRACT Energy efficiency has emerged as one of the key performance metrics in scientific computing. In this work, we evaluate the energy efficiency of floating point matrix multiplication on the state-of-the-art FPGAs. We implement a modular design parameterized with the problem size and the type of on-chip storage. To understand the efficiency of our implementations, we estimate the peak energy efficiency of any matrix multiplication implementation. Our on-chip matrix multiplication core achieves up to 7.07 and 2.28 GFlops/Joule for single and double precision arithmetic, respectively. Our implementations sustain up to 73% and 84% of the peak energy efficiency for single and double precision arithmetic, respectively. Using an optimal on-chip matrix multiplication core, we also model and estimate the energy efficiency of large-scale matrix multiplication using external DRAM. Our designs for large-scale matrix multiplication achieve energy efficiency of 5.21 and 1.60 GFlops/Joule for single and double precision, respectively.

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