Yves Berviller

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Papers by Yves Berviller

Detection d'elements en approche dans une zone mobile par vision artificielle et applications

Http Www Theses Fr, 1998

Outil de partitionnement temporel pour la conception de systèmes reconfigurables embarqués de traitement du signal

Ts Traitement Du Signal, 2005

Proposition of Temporal Partitioning Methodology for Optimization of Run- Time-Reconfiguration Implementation of data-path in FPGA

In this paper, we propose a temporal partitioning method which minimizes logic resources that a t... more In this paper, we propose a temporal partitioning method which minimizes logic resources that a time-constrained algorithm can accommodate. This analysis demonstrates how one would attack the problem of partitioning a particular algorithm into pieces for run time reconfiguration execution on FPGA. Our method consists, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. Thus, we deduce the number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation.

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Vers un partitionnement heuristique pour le mapping de data : path sur FPGA reconfiguré dynamiquement

Le problème traite du partitionnement temporel des algorithmes de TSI ayant une contrainte temps ... more Le problème traite du partitionnement temporel des algorithmes de TSI ayant une contrainte temps réel, en vue de leurs implantations optimisées sur architecture reconfigurable dynamiquement. Nous présentons une méthode, pouvant être appliquée heuristiquement, pour déterminer les étapes de la reconfiguration dynamique (RD) et un partitionnement adapté à l'implantation d'un data-path (chemin de données). L'évaluation de certaines caractéristiques liées à la technologie et la proposition d'une méthode appliquée heuristiquement, nous permettent un partitionnement optimisant les ressources matérielles en RD.

Partitionnement automatique optimisant les ressources FPGA pour l'aide à la conception de SoC reconfigurable

- Nous proposons un outil permettant d'aider les concepteurs lors de la mise en place d'a... more - Nous proposons un outil permettant d'aider les concepteurs lors de la mise en place d'algorithmes utilisant la reconfiguration dynamique. Il permet de trouver la meilleure adéquation entre une application et son implantation sur un SOC reconfigurable. Reposant sur un partitionnement temporel original, il vise différents objectifs : minimisation des ressources logiques et minimisation de la bande passante mémoire.

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Hardware partitioning software for dynamically reconfigurable SoC design

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings., 2003

CAD tools support is essential in the success of today digital system design methodologies. Unfor... more CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibilities of reconfiguration that the FPGA component can offer. Here, we present a temporal hardware partitioning software, included in a design methodology, that uses the reconfiguration possibilities of the FPGA for the SOC system design. This automated partitioning tool minimises the number of cells needed to implement an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resource needs. It can also be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field. Index Terms-FPGA -Dynamic Reconfiguration -RTR -SOC.

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Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation

Lecture Notes in Computer Science, 2000

In this paper, we present a method to estimate the number of reconfiguration steps that a time-co... more In this paper, we present a method to estimate the number of reconfiguration steps that a time-constrained algorithm can accommodate. This analysis demonstrates how one would attack the problem of partitioning a particular algorithm into pieces to for run time reconfiguration execution on a Atmel 40K FPGA. Our method consist in evaluating algorithm operators execution time from data flow graph. So, we deduce the reconfiguration number and the algorithm partitioning for RTR implementation. The algorithm used in this work, is a qualitative motion estimator in the Log-Polar plane.

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FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding

2009 IEEE International SOC Conference (SOCC), 2009

ABSTRACT Scalable video coding extension of H.264 standard is very suitable for content adaptatio... more ABSTRACT Scalable video coding extension of H.264 standard is very suitable for content adaptation and addressing different terminals. However, in various cases it is necessary to perform transcoding in video coding layer requiring tremendous computation and hardware acceleration. In this paper, we present an efficient hardware architecture of a CAVLC codec based on a new method that provides a constant and reduced latency. The presented method calculates the 16 DCT coefficients in parallel. The results of hardware implementation targeting a Xilinx Virtex 5 FPGA are presented.

Automated RTR temporal partitioning for reconfigurable embedded real-time system design

Proceedings International Parallel and Distributed Processing Symposium, 2003

We present an automated temporal partitioning applied on the data-path part of an algorithm for t... more We present an automated temporal partitioning applied on the data-path part of an algorithm for the reconfigurable embedded system design. This temporal partitioning, included in a design space exploration methodology, uses trade-offs in time constraint, design size and FPGA device parameters (circuit speed, reconfiguration time). The originality of this partitioning is that it minimize the number of cells needed to implement the data-path of an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resources needed. This optimizing approach can be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.

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Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system

Microprocessors and Microsystems, 2003

In this paper we present a new temporal partitioning methodology used for the data-path part of a... more In this paper we present a new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design. This temporal partitioning uses an assessing trade-offs in time constraint, design size and field programmable gate arrays device parameters (circuit speed, reconfiguration time). The originality of our method is that we use the dynamic reconfiguration in order to minimize the number of cells needed to implement the data-path of an application under a time constraint. Our method consists, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. Thus, we deduce the right number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation. This method allows avoiding an oversizing of implementation resources needed. This optimizing approach can be useful for the design of an embedded device or system. Our approach is illustrated by various reconfigurable implementations of real time image processing data-path. q

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An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis

IEEE Transactions on Circuits and Systems for Video Technology, 2000

The MPEG transport stream is an extremely complex structure using interlinked tables and coded id... more The MPEG transport stream is an extremely complex structure using interlinked tables and coded identifiers to separate the programs and the elementary streams. Quality management is therefore a complicated issue and the need to identify the degree of coding degradations in terms of coding and/or transmission errors or system failures is becoming an important criterion for the evaluation of the quality of the MPEG streams. A theoretical decoder (T-STD) defines the verification process based on the proper fill level of an MPEG decoder buffers whose size is defined by the standards in order to obtain an evaluation of the MPEG stream quality.

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A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems

EURASIP Journal on Advances in Signal Processing, 2003

We provide a methodology used for the temporal partitioning of the data-path part of an algorithm... more We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. Temporal partitioning of applications for reconfigurable computing systems is a very active research field and some methods and tools have already been proposed. But all these methodologies target the domain of existing reconfigurable accelerators or reconfigurable processors. In this case, the number of cells in the reconfigurable array is an implementation constraint and the goal of an optimised partitioning is to minimise the processing time and/or the memory bandwidth requirement. Here, we present a strategy for partitioning and optimising designs. The originality of our method is that we use the dynamic reconfiguration in order to minimise the number of cells needed to implement the data path of an application under a time constraint. This approach can be useful for the design of an embedded system. Our approach is illustrated by a reconfigurable implementation of a real-time image processing data path.

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Efficient implementation of a 3-D medical imaging compression system using CAVLC

Proceedings Icip International Conference on Image Processing, 2010

... Since the application targeted for 3-D medical images, the transform block in this system inc... more

The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation

J Ucs, 2007

This article presents an architecture that encrypts data with the AES algorithm. This architectur... more This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining and dynamic total reconfiguration (DTR). The originality of our implementation is that it computes sequentially in the FPGA the Key and Cipher part of the AES algorithm. This dynamic reconfiguration implementation allows a good optimization of logic resources with a high throughput. This architecture employs only 11619 slices allowing a considerable economy of the resources and reaching a maximum throughput of 44 Gbps.

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Embedded System Design for Impedance Measurement of Multi-piezo Sensor

2010 Third International Conference on Advances in Circuits, Electronics and Micro-electronics, 2010

AbstractThis paper presents a numerical impedancemeter which allows the electric impedance of a ... more

TOSCANE: TOwards SCalable audiovisual communication networks

by Yves Berviller, E. Renan, François-xavier Coudoux, Serge Weber, and M. Gazalet

2009 Global Information Infrastructure Symposium, 2009

To optimally cope with heterogeneous end device capabilities and access network link dynamics, a ... more To optimally cope with heterogeneous end device capabilities and access network link dynamics, a novel integrated video streaming system is proposed. The TOSCANE system provides scalable video encoding, transmission, and quality monitoring and adaptation over wired (xDSL) and wireless (WiFi) access and residential networks. The various components of the system are designed for supporting both "Live" multicast and "ondemand" unicast video services.

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Transrating by frequencies selectivity for H.264/AVC intra pictures

by Yves Berviller and François-xavier Coudoux

2009 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, 2009

ABSTRACT This paper presents the results obtained in the framework of the first part of the Frenc... more ABSTRACT This paper presents the results obtained in the framework of the first part of the French ANR TOSCANE project. This project aims at developing efficient solutions for adaptation of video contents to be delivered over audiovisual networks. We present here a complete transrating scheme for incoming H.264/AVC compressed video bitstreams. The proposed solution is based on frequency selective filtering and has the main advantage to be drift-error free. Experimental results show that the algorithm gives satisfying results in terms of visual quality compared to conventional transrating methods. It has been validated using the JM reference software and then implemented into a dedicated FPGA architecture. The use of the scalable extension of the H.264/AVC standard is finally considered as the following part of the project.

Original embedded impedance analyzer for piezoelectric sensors

Sensors and Actuators A: Physical, 2012

ABSTRACT In this paper we present the design, simulation and implementation of an embedded impeda... more ABSTRACT In this paper we present the design, simulation and implementation of an embedded impedance analyzer primarily intended for use with piezoelectric transducers. It is currently set to perform complex impedance measurements above 1 Ω in the range 0–5 MHz. The method does not require the current to be measured and allows grounded transducers to be analyzed in real time. It is based on feedback control of the transducer voltage using a digital resistive network RG. Real and imaginary parts of the impedance are determined from RG and the phase during a fast frequency sweeping. The entire digital architecture is implemented in an Field Programmable Gate Array (FPGA) Stratix II board with a 100 MHz frequency clock. The system is developed in a virtual environment in which the transducer is modeled by a Butterworth van Dycke structure. The duration of the analysis is optimized in real time by adjusting the sweeping speed according to changes in RG. Further, our analyzer is tested in real time and in a real situation with two 2 MHz ultrasonic transducers. The duration of the analysis is equal to 2 ms and the measurements are accurate to within 1% within the resonant zone of the transducers.

Comparison of various strategies of implementation of the algorithm of encryption AES on FPGA

2006 IEEE International Symposium on Industrial Electronics, 2006

The data security is a significant subject for which various solutions algorithms were proposed. ... more The data security is a significant subject for which various solutions algorithms were proposed. In 2001, Advanced Encryption System (AES) was accepted like a standard FIPS. AES is a symmetrical algorithm of encoding intended to replace DES which had already shown certain faults of safety in the data protection. Since then, of many achievements on hardware and software were proposed by combining various architectures. The throughput reached go from 20 Mbps to 70 Gbps according to technology and architecture used. This article presents an architecture which can be implemented on the FPGA Xilinx XC2V6000, by applying dynamic reconfiguration and reaching a speed of execution of 43 Gbps. This architecture employs only 2xxx CLB' S allowing a considerable economy of the resources.

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Efficient implementation of a 3-D medical imaging compression system using CAVLC

2010 IEEE International Conference on Image Processing, 2010

... Since the application targeted for 3-D medical images, the transform block in this system inc... more

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